Acceleration of Multiple Precision Matrix Multiplication Based on Multi-component Floating-Point Arithmetic Using AVX2

In this paper, we report the results obtained from acceleration of multi-binary64-type multiple precision matrix multiplication with AVX2. We target double-double (DD), triple-double (TD), and quad-double (QD) arithmetic designed by certain types error-free transformation (EFT) arithmetic. Furthermore, implement SIMDized EFT functions, which simultaneously compute four binary64 numbers on x86_64 computing environment, using help them, also develop DD, TD, QD additions multiplications. addition, AVX2 load/store functions were adopted to efficiently speed up reading storing elements from/to memory. Owing these combined techniques, our implemented multiplications have been accelerated more than three times compared non-accelerated ones. Our modifies performance parallelization OpenMP.